#ifndef __CORTEXM4_H
#define __CORTEXM4_H
#include "stdtype.h"

/* system control space base address */
#define CM4_SCS_BASE 0xE000E000UL
/* itm base address */
#define CM4_ITM_BASE 0xE0000000UL
/* system control block base address */
#define CM4_SCB ((scb_type_pt)(CM4_SCS_BASE + 0x0D00UL))

/* scb interrupt control state register definitions */
#define CM4_SCB_ICSR_PENDSVSET_Pos 28                                   // SCB ICSR: PENDSVSET Position
#define CM4_SCB_ICSR_PENDSVSET_Msk (1UL << CM4_SCB_ICSR_PENDSVSET_Pos)  // SCB ICSR: PENDSVSET Mask

/* layout of SCB register */
typedef struct
{
    mx_uint32_t CPUID;          /* Offset: 0x000 (R/ ) CPUID Base Register */
    mx_uint32_t ICSR;           /* Offset: 0x004 (R/W) Interrupt Control and State Register */
    mx_uint32_t VTOR;           /* Offset: 0x008 (R/W) Vector Table Offset Register */
    mx_uint32_t AIRCR;          /* Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
    mx_uint32_t SCR;            /* Offset: 0x010 (R/W) System Control Register */
    mx_uint32_t CCR;            /* Offset: 0x014 (R/W) Configuration Control Register */
    mx_uint8_t  SHP[12];        /* Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
    mx_uint32_t SHCSR;          /* Offset: 0x024 (R/W) System Handler Control and State Register */
    mx_uint32_t CFSR;           /* Offset: 0x028 (R/W) Configurable Fault Status Register */
    mx_uint32_t HFSR;           /* Offset: 0x02C (R/W) HardFault Status Register */
    mx_uint32_t DFSR;           /* Offset: 0x030 (R/W) Debug Fault Status Register */
    mx_uint32_t MMFAR;          /* Offset: 0x034 (R/W) MemManage Fault Address Register */
    mx_uint32_t BFAR;           /* Offset: 0x038 (R/W) BusFault Address Register */
    mx_uint32_t AFSR;           /* Offset: 0x03C (R/W) Auxiliary Fault Status Register */
    mx_uint32_t PFR[2];         /* Offset: 0x040 (R/ ) Processor Feature Register */
    mx_uint32_t DFR;            /* Offset: 0x048 (R/ ) Debug Feature Register */
    mx_uint32_t ADR;            /* Offset: 0x04C (R/ ) Auxiliary Feature Register */
    mx_uint32_t MMFR[4];        /* Offset: 0x050 (R/ ) Memory Model Feature Register */
    mx_uint32_t ISAR[5];        /* Offset: 0x060 (R/ ) Instruction Set Attributes Register */
    mx_uint32_t RESERVED0[5];
    mx_uint32_t CPACR;          /* Offset: 0x088 (R/W) Coprocessor Access Control Register */
} scb_type_t, *scb_type_pt;

#endif
